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- LocationBelgium
Client Background & Position Overview
Our client is a globally recognized technology leader investing heavily in next-generation semiconductor R&D. Their European research center, located in the heart of Leuven’s innovation ecosystem, focuses on advanced chip architecture and integration solutions to support future computing and communication systems.
As part of their expanding initiative in 3DIC development, the team is seeking a highly skilled Design for Test (DFT) Engineer to lead research and implementation of cutting-edge test strategies for complex semiconductor architectures including 3DIC, memory, and analog IP.
Responsibilities
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Develop and refine DFT methodologies for digital logic chips, focusing on defect mechanisms, fault simulation, and failure diagnostics.
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Design and validate testing strategies for 3DIC chips, including defect modeling and interconnect reliability analysis.
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Conduct advanced fault simulation and failure analysis on memory (including NVM) and analog IP blocks.
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Drive system-level DFX (Design for Excellence) strategies including test insertion, failure localization, and lifecycle monitoring.
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Collaborate with cross-functional teams in device modeling, packaging, circuit design, and test to develop robust test architectures.
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Stay abreast of state-of-the-art technologies through publications and contribute to internal IP and innovation strategy.
Requirements
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Master’s degree or PhD in Electronics, Microelectronics, Communications, Semiconductor Engineering, Physics, Mathematics, or related disciplines.
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5–10 years of experience in semiconductor design, test engineering, or reliability/failure analysis; exceptional PhD-level candidates with fewer years may be considered.
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Deep knowledge of DFT technologies including MBIST, SCAN, ATPG, and related toolchains.
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Solid understanding of semiconductor processes, device structures, and their impact on defect/fault behavior.
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Demonstrated experience in digital fault simulation, memory/analog test modeling, and 3DIC/IO interconnect diagnostics.
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Proven track record in developing system-level test and protection strategies, with awareness of chip lifecycle concepts.
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Strong problem-solving abilities and experience working in multidisciplinary technical environments.
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Excellent communication skills in English; ability to collaborate within international teams is a strong asset.
Join a pioneering R&D center at the forefront of semiconductor integration and testing technologies. You’ll work on disruptive architectures that will power future computing platforms, while being part of a collaborative and intellectually stimulating environment. If you're passionate about innovation in DFT and eager
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