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Functional Verification Engineer- REMOTE
The vacancy has expired
- LocationBrasov, Romania
-
Industryelectrical engineering
Job Description
Are you passionate about electronics and want to be a part of a dynamic environment within the semiconductor industry?
You like to cooperate across boundaries and are eager to contribute with your technical know-how?
This is your chance!
Job description
In your new role you will:
- Be a key member of the verification team in all verification phases;
- Prepare the verification plan, review it with design/verification teams and peers;
- Be a hands-on contributor to module & SOC verification either from scratch, or using legacy verification environments and flows. Setup, deployment/migration and maintenance of different verification environments will be one of your responsibilities;
- Support developing top-level functional test cases using real number models and analog schematics integrated with digital designs;
- Run RTL simulations using dedicated tools.
- Focus on all-directions-reuse of the Verification Environments to be implemented;
- Contribute to process improvements, also gaining domain expertise to be able to independently validate one or more functional areas of the design;
- Develop harmonious relationship within local and cross-sites design/verification engineering teams;
- Effectively work with the wider organizational community, for continuous learning and sharing best practices across teams.
Your Profile
We believe you will be a great fit for this role if you have:
- University/Master Diploma in Electrical Engineering, Computer Science or similar field;
- 3-5 years of ASIC Design Verification experience and a deep understanding of all technical aspects of IP Verification;
- Knowledge of fundamental semiconductor principles and operation (Electronic Devices and Circuits, Electronic Circuits Fundaments);
- Knowledge of object-oriented programming languages;
- A hands-on approach to reusable/scalable verification environments, development and all verification tasks needed to achieve design verification closure
- Knowledge of verification methodologies (UVM) and various verification EDA tools;
- Familiarity with data management and version control systems;
- Good knowledge of programming and/or scripting languages (C/C++, Python, TCL or others);
- Understanding of Microprocessor Architecture is a plus;
- Knowledge of digital design simulation/verification tools is a plus;
- Advanced level of English.
Benefits
- Coaching, mentoring networking possibilities;
- Wide range of training offers & planning of career development;
- International assignments;
- Different career paths: Project Management, Technical Ladder, Management & Individual Contributor;
- Flexible working hours at many sites;
- Home office options;
- Medical coverage;
- Health promotion programs;
- On-site gym with special rates;
- On-site canteens;
- Wage payment in case of sick leave based on applicable law;
- Corporate pension benefits for engineers;
- Performance bonus options;
