Our client is a leading provider of embedded control applications.The company's solutions serve more than 120,000 customers across the industrial, automotive, consumer, aerospace and defense, communications and computing markets. They are looking for a layout engineer who complete physical layout of analog and digital circuits, drawing devices per engineering instructions, running Design Rule Check (DRC) and Layout versus Schematic (LVS) checks, making plots and completing documentation.

This position will expose you to analog and digital circuits, DRC and Layout vs Schematic checks.

 

Requirements:

1. Degree in Electronics, Automatics or Electrical Engineering;
2. Should have min. 2-3 years experience in layout of CMOS logic, analog circuits, and chip-level products;
3. Should have good knowledge of English;
4. Good communication skills;
5. Analog / memory layout experience or knowledge is a plus

Responsibilities:

1. Active participate in layout design of modules and mixed signal memory products;
2. Perform layout of the analog modules using Cadence tools;
3. Performs top level floor planning, effort estimation, area optimization, project planning, and verification of analog, mixed-signal IC circuits;
4. Perform verification of layout adherence to design rules as well as Layout-vs-Schematic checks, ERC checks as well as parasitic extractions using specific tools from various vendors (Cadence, Synopsys, Mentor Graphics);
5. Performs quality checks at block level as well as chip level according to specific ISO/TS rules implemented in the company;
6. Occasional travel to the US for short period.

Benefits:

1. Attractive salary;
2. Stock options.

Place of work: Bucharest, Romania