Our Client is hiring a Senior Verification Engineer to join the Bluetooth Design Verification Team. If you are an experienced professional in the verification field, with a strong interest in innovation, come on board and join us.

Job description

As a Senior Verification Engineer , you will play a key role in technological progress. In addition, you will be responsible for a wide variety of advanced verification tasks, working closely with other teams.

In your new role you will:
 

• Be a key member of the verification team in both IP & SoC level verification phases;

• Contribute to process improvements, also gaining domain expertise to be able to independently validate one or more functional areas of the design;

• Be a hands-on contributor to IP & SOC verification either from scratch, or using legacy verification environments and flows. Setup, deployment/migration and maintenance of different verification environments will be one of your responsibilities;

• Work closely with IP designers, verification and software teams to collect, define and refine requirements for verification, prepare the verification plans, review them with design/SW teams and peers;

• Focus on all-directions-reuse of the Verification Environments to be implemented;

• Develop harmonious relationship within local and cross-sites design/verification engineering teams;

• Effectively work with the wider organizational community, for continuous learning and sharing best practices across teams.

Your Profile

You are passionate about the latest technologies and use them effectively to get the job done. Moreover, you are a true team player, acting lean and fast and striving for continuous improvement.

You are best equipped for this task if you have:
 

• 7+ years of ASIC Design Verification experience and a deep understanding of all technical aspects of IP Verification;

• A hands-on approach to reusable/scalable verification environments, development and all verification tasks needed to achieve design verification closure

• In-depth knowledge of verification methodologies (UVM, ABV, formal) and various verification EDA tools;

• A rich expertise in HVLs, such as SystemVerilog (preferred) or Specman e;

• Familiarity with data management and version control systems;

• Good knowledge of programming and/or scripting languages (C/C++, Python, Cshell, TCL or others);

• Problem solver with an innovative mindset;

• Fluency in English.

Benefits

• Coaching, mentoring networking possibilities;

• Wide range of training offers & planning of career development;

• International assignments;

• Different career paths: Project Management, Technical Ladder, Management & Individual Contributor;

• Flexible working hours at many sites;

• Home office options;

• Medical coverage;

• Health promotion programs;

• On-site gym with special rates;

• On-site canteens;

• Wage payment in case of sick leave based on applicable law;

• Corporate pension benefits for engineers;

• Performance bonus options;