Description:

Reporting to the Engineering Manager you will be part of our team. As a Layout Engineer, you will complete the physical layout of analog and digital circuits. Drawing devices per engineering instructions, running Design Rule Check (DRC) and Layout versus Schematic (LVS) checks, making plots and completing documentation.
 

What’s attractive about this opportunity?
 

This position will expose you to analog and digital circuits, DRC and Layout vs Schematic checks.
 

More details on the expectations and responsibilities in this position:
 

• Design team member who is an active participate in layout design of modules and mixed signal memory products
• Perform layout of the analog modules using Cadence tools
• Performs top level floor planning, effort estimation, area optimization, project planning, and verification of analog, mixed-signal IC circuits
• Perform verification of layout adherence to design rules as well as Layout-vs-Schematic checks, ERC checks as well as parasitic extractions using specific tools from various vendors (Cadence, Synopsys, Mentor Graphics)
• Performs quality checks at block level as well as chip level according to specific ISO/TS rules implemented in Microchip
• Occasional travel to the US for short periods
   

Qualifications and Experience:
 

• Degree in Electronics, Automatics or Electrical Engineering
• Should have a minimum of 5 years experience in layout of CMOS logic, analog circuits, and chip-level products
  
   

 Competencies:
 

• Should have good knowledge of English and good communication skills
• Analog / memory layout experience or knowledge is a plus